1. Field of the Invention
The present invention relates to signal distribution within an electronic system, and more particularly to reducing the timing skew between localized versions of a signal distributed within an electronic system.
2. Description of the Related Art
As a signal is distributed within an electronic system, the signal does not necessarily arrive at all localized destination points at the same time. This is known as timing skew, which can be a serious performance limiting problem for board-level systems as well as for integrated circuit (IC) systems. As an example, timing skews between localized versions of a clock signal within an integrated circuit arise from several underlying effects, including IR drops in the clock lines themselves or in the power supply lines, local temperature differences across the system, interconnect RC delays, clock signal loading differences, and process fluctuations across the integrated circuit (i.e., the "chip"). The aggregate effect of such factors may easily result in a clock skew of from 1-2 ns across a large integrated circuit. If the integrated circuit is desired to operate at 200 Mhz, the resulting clock cycle time is only 5 ns. Such a skew represents 20-40% of the desired system clock cycle and results in a unacceptably large performance penalty. Traditionally, systems designers have budgeted only 15% of the clock cycle for clock signal timing skew.
Referring now to FIG. 1, a signal distribution network 100 is shown for distributing a clock signal (generated by clock generator 130) throughout an integrated circuit (not shown). As one can readily recognize, the signal distribution network 100 is arranged in a hierarchical arrangement of H-shaped signal lines to try to reduce the skew between the arrival time of the signal at the terminus of each localized signal line. Such a signal distribution network 100 is termed an H-distribution tree.
Consider the case when each leg of the H-distribution tree is perfectly matched. The clock signal from clock generator 130 should arrive at any pair of symmetrically corresponding locations on the signal distribution network 100 at the same time (i.e., with no timing skew). Locations 120a and 120b (collectively, location 120) represent symmetrically corresponding locations, as the clock signal line splits in the center of the integrated circuit and the lengths of the split lines are the same. Likewise, locations 122a and 122b, locations 124a and 124b each represent symmetrically corresponding locations. Moreover, locations 110a and 110b, locations 110a and 112a, and 112a and 114a also represent symmetrically corresponding locations within the signal distribution network 100.
Traditionally, timing skews in such a signal distribution network 100 are controlled by carefully matching clock buffers to the clock loading within each section of the integrated circuit. For example, a buffer (not shown) driving the clock signal to section 102a is scaled to a buffer (not shown) driving the clock signal to section 102b. Each increasingly larger section is similarly scaled. For example, a buffer (not shown) driving the clock signal to sections 102a and 102b (collectively, section 102) is scaled to a buffer (not shown) driving the clock signal to sections 104a and 104b. Likewise, a buffer (not shown) driving the clock signal to sections 102 and 104 is scaled to a buffer (not shown) driving the clock signal to section 106.
In reality, such a perfectly matched signal distribution network 100 is difficult, if not impossible, to achieve for the reasons noted above, and clock skew is inevitable. Such clock skews limit the maximum clock frequency achievable for digital systems, especially large digital systems, and hence the performance achievable. What is needed for increasing performance of digital electronic systems is a technique for reducing timing skew between localized signals, such as clock signals, which are widely distributed across an electronic system.